1. Field of the Invention
The present invention relates generally to a multi-chip memory device, and more particularly to a multi-chip memory device formed from a stacked plurality of memory chips. The invention also relates to a method of stacking the plurality of memory chips to form the multi-chip memory device, and a method of controlling the operation of the multi-chip memory device.
2. Description of the Related Art
As electronic portable products have become smaller in size, constituent semiconductor devices within the products have generally become smaller and lighter while providing enhanced functionality. One approach to reducing the area occupied by finished semiconductor packages involves fabricating such packages to include a stacked plurality of semiconductor chips. In the case of multi-chip semiconductor devices, a plurality of memory chips are stacked one on top of the other to provide increased data storage capacity and/or available data bandwidth per unit surface area occupied by the device. Additionally or alternately, memory chips and non-memory chips may be combined in a single stacked package to implement multiple system or sub-system functionality.
In this context, the term “stacked” refers broadly to a class of semiconductor devices that vertically mount one semiconductor chip (e.g., a naked semiconductor die or a partially or fully packaged die) on top of another. The designated “vertical” orientation of the resulting stack is merely a relative term drawn in relation to an assumed horizontal disposition of a principal plane defined by the substrate implementing a semiconductor chip.
In the context of a stacked memory device, multiple memory chips may be stacked one on top of the other or multiple memory chips may be stacked on a corresponding interface chip that implements certain control functions associated with the communication (read/write(or program)/erase) of data to/from one or more of the stacked memory chips.
Memory chips may be stacked mounted one on top of the other using a number of different connection techniques. For example, when stacking first and second memory chips, each memory chip may include a pad that is electrically connected to a bonding wire. This connection technique is quite common in conventional multi-chip package memories.
Alternately, these memory chips may be stacked mounted one on top of the other using so-called “through silicon via” (TSV) techniques. As is conventionally understood, TSVs may be formed through respective semiconductor chip substrates to implement serial and/or parallel signal paths traversing part or all of a stacked plurality of semiconductor chips.